SH7137 Datasheet, PDF (162/1160 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 7 User Break Controller (UBC)
7.3.11 Break Control Register (BRCR)
BRCR sets the following conditions:
1. Specifies whether channels A and B conditions are used as two independent conditions or as
the sequential condition.
2. Specifies whether a user break is set before or after instruction execution.
3. Specifies whether to include the number of execution times in channel B comparison
conditions.
4. Specifies whether to include data bus in channels A and B comparison conditions.
5. Enables PC trace.
6. Selects the pulse width of the UBCTRG output.
7. Specifies whether to request a user break interrupt on a match of channels A and B comparison
conditions.
BRCR is a 32-bit readable/writable register that has break conditions match flags and bits for
setting a variety of break conditions.
Bit: 31 30 29 28 27 26 25
-
-
-
-
-
-
-
Initial value: 0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
Bit: 15 14 13 12 11 10 9
SCM
FCA
SCM
FCB
SCM
FDA
SCM
FDB
PCTE PCBA
-
Initial value: 0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R
24 23 22 21 20 19 18 17 16
-
-
-
UTRGW[1:0] UBIDB - UBIDA -
0
0
0
0
0
0
0
0
0
R
R
R R/W R/W R/W R R/W R
8
7
6
5
4
3
2
- DBEA PCBB DBEB -
SEQ
-
0
0
0
0
0
0
0
R R/W R/W R/W R R/W R
1
0
- ETBE
0
0
R R/W
Rev. 2.00 Sep. 10, 2008 Page 136 of 1130
REJ09B0402-0200