SH7137 Datasheet, PDF (533/1160 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 12 Port Output Enable (POE)
Initial
Bit
Bit Name value R/W Description
14 to 
10
All 0
R
Reserved
These bits are always read as 0. The write value should
always be 0.
9
OCE2
0
R/W*² Output Short High-Impedance Enable 2
This bit specifies whether to place the pins in the high-
impedance state when the OSF2 bit in OCSR2 is set to 1.
0: Does not place the pins in the high-impedance state
1: Places the pins in the high-impedance state
8
OIE2
0
R/W Output Short Interrupt Enable 2
This bit enables or disables interrupt requests when the
OSF2 bit in OCSR2 is set to 1.
0: Interrupt requests disabled
1: Interrupt requests enabled
7 to 0 
All 0
R
Reserved
These bits are always read as 0. The write value should
always be 0.
Notes: 1. Writing 0 to this bit after reading it as 1 clears the flag and is the only allowed way.
2. Can be modified only once after a power-on reset.
Rev. 2.00 Sep. 10, 2008 Page 507 of 1130
REJ09B0402-0200