SH7137 Datasheet, PDF (526/1160 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 12 Port Output Enable (POE)
Initial
Bit Bit Name value R/W Description
8
PIE1
0
R/W Port Interrupt Enable 1
This bit enables/disables interrupt requests when any one
of the POE0F to POE2F bits of the ICSR1 is set to 1.
0: Interrupt requests disabled
1: Interrupt requests enabled
7, 6 
All 0 R
Reserved
5, 4 POE2M[1:0] 00
R/W*²
These bits are always read as 0. The write value should
always be 0.
POE2 mode 1, 0
These bits select the input mode of the POE2 pin.
00: Accept request on falling edge of POE2 input
01: Accept request when POE2 input has been sampled
for 16 Pφ/8 clock pulses and all are low level.
10: Accept request when POE2 input has been sampled
for 16 Pφ/16 clock pulses and all are low level.
3, 2 POE1M[1:0] 00
R/W*²
11: Accept request when POE2 input has been sampled
for 16 Pφ/128 clock pulses and all are low level.
POE1 mode 1, 0
These bits select the input mode of the POE1 pin.
00: Accept request on falling edge of POE1 input
01: Accept request when POE1 input has been sampled
for 16 Pφ/8 clock pulses and all are low level.
10: Accept request when POE1 input has been sampled
for 16 Pφ/16 clock pulses and all are low level.
11: Accept request when POE1 input has been sampled
for 16 Pφ/128 clock pulses and all are low level.
Rev. 2.00 Sep. 10, 2008 Page 500 of 1130
REJ09B0402-0200