SH7137 Datasheet, PDF (543/1160 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 12 Port Output Enable (POE)
12.4.1 Input Level Detection Operation
If the input conditions set by ICSR1 to ICSR3 occur on the POE0 to POE2, POE4 to POE6, and
POE8 pins, the large current pins and the pins for channel 0 of the MTU2 are placed in the high-
impedance state. Note however, that these large current pins and MTU2 pins enter high-
impedance state only when general input/output function, MTU2 function, or MTU2S function is
selected for these pins.
(1) Falling Edge Detection
When a change from a high to low level is input to the POE0 to POE2, POE4 to POE6, and POE8
pins, the large current pins and the pins for channel 0 of the MTU2 are placed in the high-
impedance state. Figure 12.2 shows a sample timing after the level changes in input to the POE0
to POE2, POE4 to POE6, and POE8 pins until the respective pins enter high-impedance state.
Pφ
POE input
Pφ rising edge
Falling edge detection
PE9/TIOC3B
High-impedance state*
Note: * Other large current pins also enter the high-impedance state with the same timing.
Figure 12.2 Falling Edge Detection
Rev. 2.00 Sep. 10, 2008 Page 517 of 1130
REJ09B0402-0200