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SH7137 Datasheet, PDF (919/1160 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family
Section 22 Flash Memory
Table 22.5 Register/Parameter and Target Mode
Initiali- Program-
RAM
Download zation ming
Erasure Read Emulation
Programming/ FCCS
√
erasing interface FPCS
√
registers
PECS
√















FKEY
√

√
√


FMATS 

√*1
√*1
√*2

FTDAR √





Programming/ DPFR
√
erasing interface FPFR

parameters
FPEFEQ 


√
√
√




√





FUBRA 
√




FMPAR 

√



FMPDR 

√



FEBS



√


RAM emulation RAMER 




√
Notes: 1. The setting is required when programming or erasing user MAT in user boot mode.
2. The setting may be required according to the combination of initiation mode and read
target MAT.
Rev. 2.00 Sep. 10, 2008 Page 893 of 1130
REJ09B0402-0200