SH7137 Datasheet, PDF (181/1160 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 7 User Break Controller (UBC)
7. User breaks are disabled during UBC module standby mode. Do not read from or write to the
UBC registers during UBC module standby mode; the values are not guaranteed.
8. Do not set a post-execution break at a SLEEP instruction or a branch instruction for which a
SLEEP instruction is placed in the delay slot. In addition, do not set a data access break at a
SLEEP instruction or one or two instructions before a SLEEP instruction.
9. The UBC cannot detect external space accesses by the CPU on the I bus correctly when the
DTC is in operation. Select all bus masters when determining an external space access on the I
bus in the above condition. In this case, conditions for an identified bus master cannot be set.
However, if the bus master can be inferred from the data value, the bus master can be inferred
by including the data as a match condition.
Rev. 2.00 Sep. 10, 2008 Page 155 of 1130
REJ09B0402-0200