SH7137 Datasheet, PDF (790/1160 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 19 Controller Area Network (RCAN-ET)
Bit[15:0]: RFPR0
0
1
Description
[Clearing Condition] Writing '1' (Initial value)
Corresponding Mailbox received Remote Frame
[Setting Condition] Completion of remote frame receive in corresponding
mailbox
(7) Mailbox Interrupt Mask Register (MBIMR)
The MBIMR1 and MBIMR0 are 16-bit read / write registers. The MBIMR only prevents the
setting of IRR related to the Mailbox activities, that are IRR[1] – Data Frame Received Interrupt,
IRR[2] – Remote Frame Request Interrupt, IRR[8] – Mailbox Empty Interrupt, and IRR[9] –
Message OverRun/OverWrite Interrupt. If a mailbox is configured as receive, a mask at the
corresponding bit position prevents the generation of a receive interrupt (IRR[1] and IRR[2] and
IRR[9]) but does not prevent the setting of the corresponding bit in the RXPR or RFPR or UMSR.
Similarly when a mailbox has been configured for transmission, a mask prevents the generation of
an Interrupt signal and setting of an Mailbox Empty Interrupt due to successful transmission or
abortion of transmission (IRR[8]), however, it does not prevent the RCAN-ET from clearing the
corresponding TXPR/TXCR bit + setting the TXACK bit for successful transmission, and it does
not prevent the RCAN-ET from clearing the corresponding TXPR/TXCR bit + setting the
ABACK bit for abortion of the transmission.
A mask is set by writing a '1' to the corresponding bit position for the mailbox activity to be
masked. At reset all mailbox interrupts are masked.
• MBIMR0
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
MBIMR0[15:0]
Initial value: 1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit 15 to 0 — Enable or disable interrupt requests from individual Mailbox-15 to Mailbox-0
respectively.
Bit[15:0]: MBIMR0 Description
0
Interrupt Request from IRR1/IRR2/IRR8/IRR9 enabled
1
Interrupt Request from IRR1/IRR2/IRR8/IRR9 disabled (initial value)
Rev. 2.00 Sep. 10, 2008 Page 764 of 1130
REJ09B0402-0200