SH7137 Datasheet, PDF (662/1160 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 15 Synchronous Serial Communication Unit (SSU)
Start
[1]
[2]
Initial setting
Read SSSR
No
RDRF = 1?
Yes
ORER = 1?
Yes [3]
No
No
Consecutive data reception?
Yes
Read received data in SSRDR
RDRF automatically cleared
[1] Initial setting:
Specify the receive data format.
[2] Start reception:
When setting the RE bit to 1, reception is started.
[3], [5] Receive error processing:
When a receive error occurs, execute the designated error
processing after reading the ORER bit in SSSR. After that,
clear the ORER bit to 0. While the ORER bit is set to 1,
transmission or reception is not resumed.
[4] To complete reception:
To complete reception, read receive data after clearing the
RE bit to 0. When reading SSRDR without clearing the RE
bit, reception is resumed.
[4]
RE = 0
Read receive data in SSRDR
End reception
[5]
Overrun error processing
Clear ORER in SSSR
End reception
Note: Hatching boxes represent SSU internal operations.
Figure 15.16 Flowchart Example of Data Reception
(Clock Synchronous Communication Mode)
(4) Data Transmission/Reception
Figure 15.17 shows a flowchart example of simultaneous transmission/reception. The data
transmission/reception is performed combining the data transmission and data reception as
mentioned above. The data transmission/reception is started by writing transmit data to SSTDR
with TE = RE = 1.
Rev. 2.00 Sep. 10, 2008 Page 636 of 1130
REJ09B0402-0200