SH7137 Datasheet, PDF (530/1160 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 12 Port Output Enable (POE)
Bit Bit Name
13
POE5F
12
POE4F
11 to 9 
Initial
value
0
0
All 0
R/W Description
R/(W)*¹ POE5 Flag
This flag indicates that a high impedance request has
been input to the POE5 pin.
[Clearing conditions]
• By writing 0 to POE5F after reading POE5F = 1
(when the falling edge is selected by bits 3 and 2 in
ICSR2)
• By writing 0 to POE5F after reading POE5F = 1 after
a high level input to POE5 is sampled at Pφ/8, Pφ/16,
or Pφ/128 clock (when low-level sampling is selected
by bits 3 and 2 in ICSR2)
[Setting condition]
• When the input condition set by bits 3 and 2 in ICSR2
occurs at the POE5 pin
R/(W)*¹ POE4 Flag
This flag indicates that a high impedance request has
been input to the POE4 pin.
[Clearing conditions]
• By writing 0 to POE4F after reading POE4F = 1
(when the falling edge is selected by bits 1 and 0 in
ICSR2)
• By writing 0 to POE4F after reading POE4F = 1 after
a high level input to POE4 is sampled at Pφ/8, Pφ/16,
or Pφ/128 clock (when low-level sampling is selected
by bits 1 and 0 in ICSR2)
[Setting condition]
• When the input condition set by bits 1 and 0 in ICSR2
occurs at the POE4 pin
R
Reserved
These bits are always read as 0. The write value should
always be 0.
Rev. 2.00 Sep. 10, 2008 Page 504 of 1130
REJ09B0402-0200