SH7137 Datasheet, PDF (239/1160 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 9 Bus State Controller (BSC)
Initial
Bit
Bit Name Value R/W Description
18

0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
17, 16 IWRRS[1:0] 11
R/W Specification for Idle Cycles between Read-Read
Cycles in the Same Space
Specify the number of idle cycles to be inserted after
access to memory that is connected to the space. The
target cycles are continuous read-read cycles in the
same space.
00: No idle cycle inserted
01: 1 idle cycle inserted
10: 2 idle cycles inserted
11: 4 idle cycles inserted
15 to 11 
All 0 R
Reserved
These bits are always read as 0. The write value should
always be 0.
10, 9 BSZ[1:0] 01/11* R/W Data Bus Size Specification
Specify the data bus size of the space. When the on-
chip ROM is enabled, write B'01 to specify the data bus
width as 8-bit before accessing the CSn space.
Note: When the on-chip ROM is disabled, the data bus
width of area 0 is 8 bits regardless of the
BSZ[1:0] bit setting in CS0BCR.
8 to 0 
All 0 R
Reserved
These bits are always read as 0. The write value should
always be 0.
Note: * B'01 when the on-chip ROM is disabled.
Rev. 2.00 Sep. 10, 2008 Page 213 of 1130
REJ09B0402-0200