SH7137 Datasheet, PDF (82/1160 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 4 Clock Pulse Generator (CPG)
Figure 4.1 shows a block diagram of the clock pulse generator.
Oscillator unit
MTU2S clock
(MIφ)
XTAL
EXTAL
Oscillation
stop detection
Crystal
oscillator
Oscillation stop
detection circuit
PLL circuit
(×8)
Divider
×1
×1/2
×1/3
×1/4
×1/8
MTU2 clock
(MPφ)
Internal clock
(Iφ)
Peripheral clock
(Pφ)
CK
Clock frequency
control circuit
CPG control unit
Standby
control circuit
Bus clock
(Bφ = CK)
OSCCR
FRQCR
STBCR1 STBCR2 STBCR3 STBCR4 STBCR5 STBCR6
Bus interface
[Legend]
FRQCR:
OSCCR:
STBCR1:
STBCR2:
STBCR3:
STBCR4:
STBCR5:
STBCR6:
Frequency control register
Oscillation stop detection control register
Standby control register 1
Standby control register 2
Standby control register 3
Standby control register 4
Standby control register 5
Standby control register 6
Internal bus
Figure 4.1 Block Diagram of Clock Pulse Generator
Rev. 2.00 Sep. 10, 2008 Page 56 of 1130
REJ09B0402-0200