SH7137 Datasheet, PDF (667/1160 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 16 I²C Bus Interface 2 (I²C2)
Section 16 I²C Bus Interface 2 (I²C2)
The I²C bus interface 2 conforms to and provides a subset of the Philips I²C (Inter-IC) bus
interface functions. However, the configuration of the registers that control the I²C bus differs
partly from the Philips register configuration.
Figure 16.1 shows a block diagram of the I²C bus interface 2. Figure 16.2 shows an example of
I/O pin connections to external circuits.
16.1 Features
• Selection of I²C format or clock synchronous serial format
• Continuous transmission/reception
Since the shift register, transmit data register, and receive data register are independent from
each other, the continuous transmission/reception can be performed.
• Module standby mode can be set
I²C bus format:
• Start and stop conditions generated automatically in master mode
• Selection of acknowledge output levels when receiving
• Automatic loading of acknowledge bit when transmitting
• Bit synchronization function
In master mode, the state of SCL is monitored per bit, and the timing is synchronized
automatically.
If transmission/reception is not yet possible, set the SCL to low until preparations are
completed.
• Six interrupt sources
Transmit data empty (including slave-address match), transmit end, receive data full (including
slave-address match), arbitration lost, NACK detection, and stop condition detection
The data transfer controller (DTC) can be activated by a transmit-data-empty request or
receive-data-full request to transfer data.
• Direct bus drive
Two pins, SCL and SDA pins, function as NMOS open-drain outputs when the bus drive
function is selected.
Rev. 2.00 Sep. 10, 2008 Page 641 of 1130
REJ09B0402-0200