SH7137 Datasheet, PDF (546/1160 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 12 Port Output Enable (POE)
12.5 Interrupts
The POE issues a request to generate an interrupt when the specified condition is satisfied during
input level detection or output level comparison. Table 12.5 shows the interrupt sources and their
conditions.
Table 12.5 Interrupt Sources and Conditions
Name
OEI1
OEI2
OEI3
Interrupt Source
Output enable interrupt 1
Output enable interrupt 2
Output enable interrupt 3
Interrupt Flag
POE2F, POE1F, POE0F,
and OSF1
POE8F
POE4F, POE5F, POE6F,
and OSF2
Condition
PIE1 • (POE2F + POE1F +
POE0F) + OIE1 • OSF1
PIE3 • POE8F
PIE2 • (POE4F + POE5F +
POE6F) + OIE2 • OSF2
12.6 Usage Note
12.6.1 Pin State when a Power-On Reset is Issued from the Watchdog Timer
When a power-on reset is issued from the watchdog timer (WDT), initialization of the pin function
controller (PFC) sets initial values that select the general input function for the I/O ports.
However, when a power-on reset is issued from the WDT while a pin is being handled as high
impedance by the port output enable (POE), the pin is placed in the output state for one cycle of
the peripheral clock (Pf), after which the function is switched to general input.
This also occurs when a power-on reset is issued from the WDT for pins that are being handled as
high impedance due to short-circuit detection by the MTU2 and MTU2S.
Figure 12.5 shows the state of a pin for which the POE input has selected high impedance
handling with the timer output selected when a power-on reset is issued from the WDT.
Rev. 2.00 Sep. 10, 2008 Page 520 of 1130
REJ09B0402-0200