SH7137 Datasheet, PDF (33/1160 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family

1.2 Block Diagram
The block diagram of SH7136 and SH7137 is shown in figure 1.1.
SH2
CPU
UBC
L bus (Iφ)
Section 1 Overview
ROM
RAM
Internal bus
controller
I bus (Bφ)
BSC
Peripheral bus
controller
DTC
External bus
Peripheral bus (Pφ)
I/O
port
(PFC)
SCI CMT INTC Power- WDT CPG MTU2 MTU2S POE SSU ADC RCAN-ET H-UDI I²C2
down
mode
control
[Legend]
ROM:
RAM:
UBC:
INTC:
CPG:
WDT:
CPU:
BSC:
DTC:
On-chip ROM
On-chip RAM
User break controller
Interrupt controller
Clock pulse generator
Watchdog timer
Central processing unit
Bus state controller
Data transfer controller
PFC:
Pin function controller
MTU2: Multi-function timer pulse unit 2
MTU2S: Multi-function timer pulse unit 2 (subset)
POE:
Port output enable
SCI:
Serial communication interface
SSU:
Synchronous serial communication unit
CMT:
Compare match timer
ADC:
A/D converter
RCAN-ET: Controller area network
I²C2:
I²C Bus interface 2
H-UDI: User debugging interface
Figure 1.1 Block Diagram
Rev. 2.00 Sep. 10, 2008 Page 7 of 1130
REJ09B0402-0200