JG82852GMSL7VP Datasheet, PDF (97/176 Pages) Intel Corporation – Intel® 852GM/852GMV Chipset Intel® 852GM/852GMV Chipset Hub (GMCH)

Register Description
R
3.10.4.
PCISTS – PCI Status Register
Address Offset:
Default Value:
Access:
Size:
06h
0080h
Read Only, Read/Write/Clear
16 bits
PCISTS is a 16-bit status register that reports the occurrence of error events on Device #0’s PCI
interface. Bit 14 is read/write clear. All other bits are Read Only. Since Intel 852GM/852GMV GMCH
Device #0 does not physically reside on PCI_A many of the bits are not implemented.
Bit
Descriptions
15
Detected Parity Error (DPE): The Intel 852GM/852GMV GMCH does not implement this bit and it is
hardwired to a 0. Writes to this bit position have no effect.
14
Signaled System Error (SSE): The Intel 852GM/852GMV GMCH does not implement this bit and it is
hardwired to a 0. Writes to this bit position have no effect.
13
Received Master Abort Status (RMAS): The Intel 852GM/852GMV GMCH does not implement this bit
and it is hardwired to a 0. Writes to this bit position have no effect.
12
Received Target Abort Status (RTAS): The Intel 852GM/852GMV GMCH does not implement this bit and
it is hardwired to a 0. Writes to this bit position have no effect.
11
Signaled Target Abort Status (STAS): The Intel 852GM/852GMV GMCH does not implement this bit and
it is hardwired to a 0. Writes to this bit position have no effect.
10:9
DEVSEL Timing (DEVT): These bits are hardwired to "00". Writes to these bit positions have no affect.
Device #0 does not physically connect to PCI_A. These bits are set to "00" (fast decode) so that the Intel
852GM/852GMV GMCH does not limit optimum DEVSEL timing for PCI_A.
8
Master Data Parity Error Detected (DPD): The Intel 852GM/852GMV GMCH does not implement this bit
and it is hardwired to a 0. Writes to this bit position have no effect.
7
Fast Back-to-Back (FB2B): This bit is hardwired to 1. Writes to these bit positions have no effect. Device
#0 does not physically connect to PCI_A. This bit is set to 1 (indicating fast back-to-back capability) so that
the Intel 852GM/852GMV GMCH does not limit the optimum setting for PCI_A.
6:5
Reserved
4
Capability List (CLIST): This bit is hardwired to 0 to indicate to the configuration software that this
device/function does not implement new capabilities.
3:0
Reserved
Intel^® 852GM/852GMV Chipset GMCH Datasheet
97