JG82852GMSL7VP Datasheet, PDF (139/176 Pages) Intel Corporation – Intel® 852GM/852GMV Chipset Intel® 852GM/852GMV Chipset Hub (GMCH)

Functional Description
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5.5.2.2.
5.5.2.3.
Depending on configuration and mode, a single channel can take 18-bits of RGB pixel data plus 3 bits of
timing control (HSYNC/VSYNC/DE) and output them on three differential data pair outputs; or 24 bits
of RGB plus 3 bits of timing control output on four differential data pair outputs. A dual channel
interface converts 36 bits or 48 bits of color information plus the 3 bits of timing control and outputs it
on six or eight sets of differential data outputs.
This display port is normally used in conjunction with the pipe functions of panel scaling and a 6-bit to
8-bit dither. This display port is also used in conjunction with the panel power sequencing and
additional associated functions.
When enabled, the LVDS constant current drivers consume significant power. Individual pairs or sets of
pairs can be selected to be powered down when not used. When disabled, individual or sets of pairs will
enter a low power state. When the port is disabled all pairs enters a low power mode. The panel power
sequencing can be set to override the selected power state of the drivers during power sequencing. For
more details on using the GMCH’s LFP LVDS interface for TFT Panel support, please refer to the
Common Panel Interface Specification, Rev 1.5 for details on:
CPIS Supported Resolutions
CPIS DC/AC Specifications
CPIS Pin Lists and Connectors
CPIS EDID Table Outline
CPIS Reference EDID Formats (XGA at 60-Hz Refresh Rate)
Sample CPIS EDID DTD’s (Primary Resolution at 60-Hz Refresh Rate)
Video Serialization Formats
References and External Standards
LVDS Interface Signals
LVDS for flat panel is compatible with the ANSI/TIA/EIA-644 specification. This is an electrical
standard only defining driver output characteristics and receiver input characteristics. There are two
LVDS transmitter channels (channel A and channel B) in the LVDS interface. Each channel consists of
four data pairs and a clock pair. The interface consists of a total of ten differential signal pairs of which
eight are data and two are clocks. The phase locked transmit clock is transmitted in parallel with the data
being sent out over the data pairs and over the LVDS clock pair.
Each channel supports transmit clock frequency ranges from 25-MHz to 112-MHz, which provides a
throughput of up to 784-Mbps on each data output and up to 112-MP/s on the input. When using both
channels, they each operate at the same frequency each carrying a portion of the data. The maximum
pixel rate is increased to 224-MP/s but may be limited to less than that due to restrictions elsewhere in
the circuit.
The LVDS Port Enable bit enables or disables the entire LVDS interface. When the port is disabled, it
will be in a low power state. Once the port is enabled, individual driver pairs will be disabled based on
the operating mode. Disabled drivers can be powered down for reduced power consumption or
optionally fixed to forced 0’s output.
LVDS Pair States
The LVDS pairs can be put into one of the following five states: powered down tri-state, powered down
Zero Volts, common mode, send zeros, or active. When in the active state, several data formats are
supported. When in powered down state, the circuit enters a low power state and drives out 0 V or tri-
states on both the output pins for the entire channel. The common mode tri-state is both pins of the pair
Intel^® 852GM/852GMV Chipset GMCH Datasheet
139