JG82852GMSL7VP Datasheet, PDF (27/176 Pages) Intel Corporation – Intel® 852GM/852GMV Chipset Intel® 852GM/852GMV Chipset Hub (GMCH)

Introduction
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Table 2. Intel 852GM/852GMV GMCH Interface Clocks
Interface
Clock Speed
CPU System Bus
Frequency Ratio
CPU Bus
100 MHz
CPU Bus
133 MHz
(852GMV Only)
DDR SDRAM
100 MHz
133 MHz
LVDS Flat Panel
DVO C
DAC Interface
25 MHz-112 MHz
(single channel)
Up to 165 MHz
350 MHz
Reference
Reference
1:1 Synchronous
1:1 Synchronous
Asynchronous
Asynchronous
Asynchronous
Samples
Per Clock
4
4
2
2
1
2
1
Data Rate
(Mega-
samples/s)
400
533
200
266
112
330
350
Data
Width
(Bytes)
8
8
8
8
2.25
1.5
3
Peak
Bandwidth
(MB/s)
3200
4264
1600
2128
252
495
1050
1.11.
System Interrupts
The Intel 852GM/852GMV GMCH supports both the legacy Intel 8259 Programmable Interrupt
delivery mechanism and the processor side bus interrupt delivery mechanism. The serial APIC Interrupt
mechanism is not supported.
The Intel 8259 Interrupt delivery mechanism support consists of flushing in bound Hub Interface write
buffers when an Interrupt Acknowledge cycle is forwarded from the system bus to the Hub Interface.
PCI MSI interrupts are generated as Memory Writes. The GMCH decodes upstream Memory Writes to
the range 0FEE0_0000h - 0FEEF_FFFFh from the Hub Interface as message based interrupts. The
GMCH forwards the Memory Writes along with the associated write data to the system bus as an
Interrupt Message transaction. Since this address does not decode as part of main System Memory, the
write cycle and the write data does not get forwarded to System Memory via the write buffer. The
GMCH provides the response and HTRDY# for all Interrupt Message cycles including the ones
originating from the GMCH. The GMCH also supports interrupt re-direction for upstream interrupt
memory writes.
For message based interrupts, system write buffer coherency is maintained by relying on strict ordering
of Memory Writes. The GMCH ensures that all Memory Writes received from a given interface prior to
an interrupt message Memory Write are delivered to the system bus for snooping in the same order that
they occur on the given interface.
Intel^® 852GM/852GMV Chipset GMCH Datasheet
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