JG82852GMSL7VP Datasheet, PDF (57/176 Pages) Intel Corporation – Intel® 852GM/852GMV Chipset Intel® 852GM/852GMV Chipset Hub (GMCH)

Register Description
R
3.8.5.
Bit
4
3:0
Descriptions
Capability List (CLIST): This bit is hardwired to 1 to indicate to the configuration software that this
device/function implements a list of new capabilities. A list of new capabilities is accessed via register
CAPPTR at configuration address offset 34h.
Default Value=1.
Reserved
RID – Register Identification
Address Offset:
Default Value:
Access:
Size:
08h
01h
Read Only
8 bits
This register contains the revision number of the GMCH Device #0. These bits are read only and writes
to this register have no effect.
3.8.6.
Bit
7:0
Descriptions
Revision Identification Number (RID): This is an 8-bit value that indicates the revision identification
number for the GMCH Device #0.
Default Value=01h
SUBC – Sub Class Code
Address Offset:
Default Value:
Access:
Size:
0Ah
00h
Read Only
8 bits
This register contains the Sub-Class Code for the GMCH Device #0. This code is 00h indicating a Host
Bridge device.
Bit
7:0
Descriptions
Sub-Class Code (SUBC): This is an 8-bit value that indicates the category of Bridge into which the GMCH
falls. The code is 00h indicating a Host Bridge.
Default Value=0
Intel^® 852GM/852GMV Chipset GMCH Datasheet
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