JG82852GMSL7VP Datasheet, PDF (75/176 Pages) Intel Corporation – Intel® 852GM/852GMV Chipset Intel® 852GM/852GMV Chipset Hub (GMCH)

Register Description
R
3.8.24.
SCICMD – SCI Error Command Register (Device 0)
Address Offset:
Default Value:
Access:
Size:
67h
00h
Read/Write
8 bits
This register enables various errors to generate a SCI Hub Interface special cycle. When an error flag is
set in the ERRSTS register it can generate a SERR, SMI, or SCI Hub Interface special cycle when
enabled in the ERRCMD, SMICMD, or SCICMD registers respectively.
Note: An error can generate one and only one Hub Interface error special cycle. It is software’s responsibility
to make sure that when an SCI error message is enabled for an error condition, SERR and SMI error
messages are disabled for that same error condition.
Bit
7:4
3
2
1
0
Description
Reserved
SCI on Intel 852GM/852GMV GMCH Thermal Sensor Trip:
1 = An SCI Hub Interface special cycle is generated by Intel 852GM/852GMV GMCH when the thermal
sensor trip requires an SCI. A thermal sensor trip point cannot generate more than one special cycle.
Reserved
SCI on Multiple-bit ECC Error:
1 = Reserved
0 = For systems that do not support ECC, this field must be set to 0 (Intel 852GM/852GMV GMCH only).
SCI on Single-bit ECC Error:
1 = Reserved
0 = For systems that do not support ECC, this field must be set to 0 (Intel 852GM/852GMV GMCH only).
3.8.25.
CAPD – Capability Disable Bits
Address Offset:
Default Value:
Access:
Size:
F4h-F7h
00000000h
Read/Write
32 bits
Bit
31:12
11:0
Descriptions
Reserved
Capability Disable bits corresponding to Capability Register 39:28. This bit is logically ORed with the
corresponding strap and result of the “OR” is read through the capability register. Note that this register
cannot be used to enhance capability.
0 = Normal Operation.
1 = Forces Corresponding Capability to be disabled.
Intel^® 852GM/852GMV Chipset GMCH Datasheet
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