JG82852GMSL7VP Datasheet, PDF (60/176 Pages) Intel Corporation – Intel® 852GM/852GMV Chipset Intel® 852GM/852GMV Chipset Hub (GMCH)

Register Description
R
3.8.12.
CAPID Capability Identification Register (Device 0)
Address Offset:
Default:
Access:
Size
40h – 44h
0F_F105_F009h
Read Only
40 bits
The Capability Identification Register uniquely identifies chipset capabilities as defined in the table
below. The bits in this register are intended to define a capability ceiling for each feature, not a
capability select. The capability selection for each feature is implemented elsewhere. The mechanism to
select the capability for each feature must comprehend these capabilities registers and not allow a
selected setting above the ceiling specified in these registers. The BIOS must read this register to
identify the SKU of the part and comprehend the capabilities specified within when configuring the
effected portions of the GMCH.
The default setting, in most cases, allows the maximum capability. Exceptions are noted in the
individual bits. This register is Read Only. Writes to this register have no effect.
Bit
39:37
36:30
29
28
27:24
23:16
15:8
7:5
4:0
Descriptions
Capability ID [2:0]:
000-100 =reserved
101= Intel 852GM/852GMV GMCH
110-111 = reserved
Reserved
0 = Reserved
1 = Device #1 and associated System Memory and IO spaces are disabled. In addition, Next_Pointer =
00h, APBASE is read only, and Aperture Global Access is Disabled.
Reserved
CAPREG Version: This field has the value 0001b to identify the first revision of the CAPREG definition.
Cap_length: This field has the value 05h indicating the structure length.
Reserved
CAP_ID:
000 = Reserved
100 = Reserved
101 = Intel 852GM/852GMV GMCH
Reserved
60
Intel^® 852GM/852GMV Chipset GMCH Datasheet