JG82852GMSL7VP Datasheet, PDF (87/176 Pages) Intel Corporation – Intel® 852GM/852GMV Chipset Intel® 852GM/852GMV Chipset Hub (GMCH)

Register Description
R
Bit
1:0
Description
DDR SDRAM RAS# Precharge (tRP): This bit controls the number of clocks that are inserted between a row
precharge command and an activate command to the same row
Encoding tRP
00:
Reserved
01:
3 DDR SDRAM Clocks
10:
2 DDR SDRAM Clocks
11:
Reserved
3.9.15. PWRMG – DRAM Controller Power Management Control
Register - Device #0
Address Offset:
Default Value:
Access:
Size:
68h-6Bh
00000000h
Read/Write
32 bits
Bit
31:24
23:20
Description
Reserved
Row State Control: This field determines the number of clocks the DDR SDRAM controller will retain in
the idle state before it begins pre-charging all pages or powering down rows.
PDEn: Power Down Enable
PCEn: Page Close Enable
TC: Timer Control
PDEn(23):
0
0
1
1
PCEn(22):
0
1
0
1
TC(21:20)Function
XX
All disabled
XX
Reserved
XX
Reserved
0X
Reserved
10
Reserved
11
Precharge and Power Down after 64 DDR SDRAM
Clocks of idle time
19:0
Intel^® 852GM/852GMV Chipset GMCH Datasheet
87