JG82852GMSL7VP Datasheet, PDF (145/176 Pages) Intel Corporation – Intel® 852GM/852GMV Chipset Intel® 852GM/852GMV Chipset Hub (GMCH)

Power and Thermal Management
R
•G2/S5 Hard off. Total reboot.
6.3. Enhanced Intel SpeedStep Technology Overview
With Enhanced Intel SpeedStep Technology the processor core voltage changes and allows true CPU
core frequency changes versus only clock throttling.
Note: Enhanced Intel Speed Step technology is not supported for Intel Celeron M processor, mobile Intel
Celeron processor and Intel Celeron D processor on 90 nm process and in the 478-pin package.
Table 30. Enhanced Intel SpeedStep Technology Overview
CPU
Mobile Intel Pentium 4 Processor-M
Benefit Over Non-power Managed CPU ^{Additional lower voltages and frequencies}
Transition Prompt
OS based on CPU load demand, thermal control, or user event based
CPU Availability
CPU unavailability can be restricted to ~250 µs (CPU dependent) by s/w
6.4.
6.4.1.
6.4.2.
Internal Thermal Sensor
This section describes the new on-die thermal sensor capability. The thermal sensor functions are
provided below:
Catastrophic Trip Point: This trip point is programmed through the BIOS during initialization. This
trip point is set at the temperature at which the GMCH should be shut down immediately with minimal
software support. The settings for this are lockable.
High Temperature Trip Point: This trip point is nominally 14ºC below the Catastrophic Trip Point.
The BIOS can be programmed to provide an interrupt when it is crossed in either direction. Upon the trip
event, hardware throttling may be enabled when the temperature is exceeded.
Hardware Throttling
The Hot trip points’ crossings events may be used to trigger throttling without intervention by software.
System Memory write throttling may be enabled on Hot trip points. The HTC register selects whether it
is Catastrophic or both that enable throttling. System Memory write throttling registers in Device #0
configuration space determine whether throttling is enabled at all.
Register Locking
TCO contains a lock bit that locks the catastrophic programming interface, including TCO, TCTS, and
two bits in TSCR that could disable the sensor or alter the trip point. HTC has a lock bit for the hardware
throttling settings.
Intel^® 852GM/852GMV Chipset GMCH Datasheet
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