JG82852GMSL7VP Datasheet, PDF (123/176 Pages) Intel Corporation – Intel® 852GM/852GMV Chipset Intel® 852GM/852GMV Chipset Hub (GMCH)

Functional Description
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5. Functional Description
5.1.
Host Interface Overview
The GMCH Processor System Bus uses source synchronous transfer for the address and data signals.
The address signals are double pumped and two addresses can be generated every bus clock. At 100-
MHz bus frequency, the two address signals run at 200-MT/s for a maximum address queue rate of 50-
M addresses/sec. The data is quad pumped and an entire 64B cache line can be transferred in two bus
clocks. At 100-MHz bus frequency, the data signals run at 400 MHz for a maximum bandwidth of 3.2-
GB/s. The 852GM/852GMV GMCH has In-Order Queue to support outstanding pipelined address
requests on the host bus.
5.2. Dynamic Bus Inversion
The GMCH supports Dynamic Bus Inversion (DBI) when driving and receiving data from the Host Bus.
DBI limits the number of data signals that are driven to a low voltage on each quad pumped data phase.
This decreases the power consumption of the GMCH. DINV[3:0] indicates if the corresponding 16 bits
of data are inverted on the bus for each quad pumped data phase:
Table 26. Relation of DBI Bits to Data Bits
DINV[3:0]
Data Bits
DINV[0]#
DINV[1]#
DINV[2]#
DINV[3]#
HD[15:0]#
HD[31:16]#
HD[47:32]#
HD[63:48]#
Whenever the CPU or the GMCH drives data, each 16-bit segment is analyzed. If more than eight of the
16 signals would normally be driven low on the bus the corresponding DINV# signal will be asserted
and the data will be inverted prior to being driven on the bus. Whenever the CPU or the GMCH receives
data it monitors DINV[3:0]# to determine if the corresponding data segment should be inverted.
5.2.1.
System Bus Interrupt Delivery
Each processor supports System Bus interrupt delivery. It does not support the APIC serial bus interrupt
delivery mechanism. Interrupt related messages are encoded on the System Bus as “Interrupt Message
Transactions”. In a GMCH platform, System Bus interrupts may originate from the processor on the
System Bus, or from a downstream device on Hub Interface.
In a GMCH platform, the ICH4-M contains IOxAPICs and its interrupts are generated as upstream Hub
Interface Memory Writes. Furthermore, PCI 2.2 defines MSI’s (Message Signaled Interrupts) that are
also in the form of Memory Writes. A PCI 2.2 device may generate an interrupt as an MSI cycle on its
PCI bus instead of asserting a hardware signal to the IOxAPIC. The MSI may be directed to the
IOxAPIC, which in turn generates an interrupt as an upstream Hub Interface Memory Write.
Alternatively the MSI may be directed directly to the System bus. The target of an MSI is dependent on
Intel^® 852GM/852GMV Chipset GMCH Datasheet
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