JG82852GMSL7VP Datasheet, PDF (73/176 Pages) Intel Corporation – Intel® 852GM/852GMV Chipset Intel® 852GM/852GMV Chipset Hub (GMCH)

Register Description
R
Bit
5
4:2
1
0
Description
SERR on Receiving Unimplemented Special Cycle Hub Interface Completion Packet:
1 = The Intel 852GM/852GMV GMCH generates an SERR Hub Interface special cycle when an Intel
852GM/852GMV GMCH initiated Hub Interface request is terminated with a Unimplemented Special
Cycle completion packet.
0 = Disable. Reporting of this condition is disabled.
Reserved
SERR on Multiple-bit ECC Error:
1 = Reserved
0 = For systems that do not support ECC, this field must be set to 0 (Intel 852GM/852GMV GMCH only).
SERR on Single-bit ECC Error:
1 = Reserved
0 = For systems that do not support ECC, this field must be set to 0 (Intel 852GM/852GMV GMCH only).
Intel^® 852GM/852GMV Chipset GMCH Datasheet
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