JG82852GMSL7VP Datasheet, PDF (40/176 Pages) Intel Corporation – Intel® 852GM/852GMV Chipset Intel® 852GM/852GMV Chipset Hub (GMCH)

Signal Description
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2.5.4. General Purpose Input/Output Signals
Table 10. Intel 852GM/852GMV GMCH GPIO (DDC, I2C, etc.) Signal Descriptions
GPIO I/F Total Type
Comments
RSTIN#
I Reset: Primary Reset
CMOS
PWROK
I Power OK: Indicates that power to GMCH is stable.
CMOS
AGPBUSY#
O
CMOS
AGPBUSY: Output of the GMCH graphics controller to the ICH4-M, which indicates that
certain graphics activity is taking place. It will indicate to the ACPI software to not enter the
C3 state. It will also cause a C3/C4 exit if C3/C4 was being entered, or was already entered
when AGPBUSY# went active. Not active when the graphics controller is in any ACPI state
other than D0.
EXTTS_0
I
CMOS
External Thermal Sensor Input: This signal is an active low input to the GMCH and is
used to monitor the thermal condition around the System Memory and is used for triggering
a read throttle. The GMCH can be optionally programmed to send a SERR, SCI, or SMI
message to the ICH4-M upon the triggering of this signal.
LCLKCTLA
O SSC Chip Clock Control: Can be used to control an external clock chip with SSC control.
CMOS
LCLKCTLB
O SSC Chip Data Control: Can be used to control an external clock chip for SSC control.
CMOS
PANELVDDEN
O LVDS Panel power control: This signal is used enable power to the panel interface.
CMOS
PANELBKLTEN O LVDS Panel backlight enable: This signal is used to enable the back light inverter(BLI).
CMOS
PANELBKLTCTL O LVDS Panel backlight brightness control: This signal is used as power control.
CMOS
DDCACLK
I/O CRT DDC Clock: This signal is used as the DDC clock signal between the CRT monitor
CMOS ^{and the GMCH.}
DDCADATA
I/O CRT DDC Data: This signal is used as the DDC data signal between the CRT monitor and
CMOS ^{the GMCH.}
DDCPCLK
I/O Panel DDC Clock: This signal is used as the DDC clock signal between the LFP and the
CMOS ^GMCH.
DDCPDATA
I/O Panel DDC Data: This signal is used as the DDC data signal between the LFP and the
CMOS ^GMCH.
MI2CCLK
I/O DVO I2C Clock: The specific function is I2C_CLK for a digital display (i.e. TV-Out Encoder,
DVO ^{TMDS transmitter). This signal is tri-stated during a hard reset.}
MI2CDATA
I/O DVO I2C Data: The specific function is I2C_DATA for a digital display (i.e. TV-Out Encoder,
DVO ^{TMDS transmitter). This signal is tri-stated during a hard reset.}
MDVICLK
I/O DVI DDC Clock: The specific function is DDC clock for a digital display connector (i.e.
DVO ^{primary digital monitor). This signal is tri-stated during a hard reset.}
MDVIDATA
I/O DVI DDC Data: The specific function is DDC data for a digital display connector (i.e.
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Intel^® 852GM/852GMV Chipset GMCH Datasheet