JG82852GMSL7VP Datasheet, PDF (71/176 Pages) Intel Corporation – Intel® 852GM/852GMV Chipset Intel® 852GM/852GMV Chipset Hub (GMCH)

Register Description
R
3.8.21.
ERRSTS – Error Status Register (Device 0)
Address Offset:
Default Value:
Access:
Size:
62–63h
0000h
Read/Write Clear
16 bits
This register is used to report various error conditions via Hub Interface special cycles. An SERR, SMI,
or SCI Error Hub Interface special cycle may be generated on a zero to one transition of any of these
flags when enabled in the PCICMD/ERRCMD, SMICMD, or SCICMD registers respectively.
Bit
15:14
13
12
11
10
9
8
7
6
5
4:0
Description
Reserved
FSB Strobe Glitch Detected (FSBAGL): When this bit is set to 1 the Intel 852GM/852GMV GMCH has
detected a glitch on one of the FSB strobes. Writing a 1 to it clears this bit.
Intel 852GM/852GMV GMCH Software Generated Event for SMI:
1 = This indicates the source of the SMI was a Device #2 Software Event.
0 = Software must write a 1 to clear this bit.
Intel 852GM/852GMV GMCH Thermal Sensor Event for SMI/SCI/SERR:
1 = Indicates that a Intel 852GM/852GMV GMCH Thermal Sensor trip has occurred and an SMI, SCI or
SERR has been generated. Note that the status bit is set only if a message is sent based on Thermal
event enables in Error command, SMI command and SCI command registers. Note that a trip point
can generate one of SMI. SCI or SERR interrupts (two or more per event is illegal). Multiple trip
points can generate the same interrupt, if software chooses this mode subsequent trips may be lost.
0 = Software must write a 1 to clear this status bit. If this bit is set then an interrupt message will not be
sent on a new thermal sensor event.
Reserved
LOCK to non-DDR SDRAM Memory Flag (LCKF)—R/WC:
1 = Indicates that a CPU initiated LOCK cycle targeting non-DDR SDRAM memory space occurred.
0 = Software must write a 1 to clear this status bit
Received Refresh Timeout—R/WC:
1 = This bit is set when 1024 memory core refresh are Queued up.
0 = Software must write a 1 to clear this status bit.
DRAM Throttle Flag (DTF)—R/WC:
1 = Indicates that the DDR SDRAM Throttling condition occurred.
0 = Software must write a 1 to clear this status bit.
Reserved
Received Unimplemented Special Cycle Hub Interface Completion Packet FLAG (UNSC)—R/WC:
1 = Indicates that the Intel 852GM/852GMV GMCH initiated a Hub Interface request that was terminated
with an Unimplemented Special Cycle completion packet.
0 = Software must write a 1 to clear this status bit.
Reserved
Intel^® 852GM/852GMV Chipset GMCH Datasheet
71