JG82852GMSL7VP Datasheet, PDF (138/176 Pages) Intel Corporation – Intel® 852GM/852GMV Chipset Intel® 852GM/852GMV Chipset Hub (GMCH)

Functional Description
5.5.
R
Display Interface
The GMCH has three dedicated display ports: the analog port, the LFP LVDS interface, and Digital
display port, DVOC. DVOC can support TV-out encoders, external DACs, LVDS transmitters, and
TMDS transmitters. Each display port has control signals that may be used to control, configure and/or
determine the capabilities of an external device. The data that is sent out the display ports are selected
from one of the two possible sources, display pipe A or display pipe B, except for the LVDS port which
can only be driven on Pipe B.
The GMCH’s digital display port is capable of driving a 165-MHz pixel clock on a single DVO port.
5.5.1.
5.5.1.1.
5.5.1.2.
Analog Display Port Characteristics
The analog display port provides an RGB signal output along with an HSYNC and VSYNC signal.
There is an associated DDC signal pair that is implemented using GPIO pins dedicated to the analog
port. The intended target device is for a CRT based monitor with a VGA connector.
Integrated RAMDAC
The display function contains a 350-MHz integrated 24-bit RAM-based Digital-to-Analog Converter
(RAMDAC) that transforms up to 1600X1200 digital pixels (Intel 852GM/852GMV GMCH) at a
maximum refresh rate of 85 Hz. Three 8-bit DACs provide the R, G, and B signals to the monitor.
DDC (Display Data Channel)
DDC is defined by VESA. It allows communication between the host system and display. Both
configuration and control information can be exchanged allowing plug-and-play systems to be realized.
Support for DDC 1 and 2 is implemented.
5.5.2.
5.5.2.1.
Digital Display Interface
Dedicated LVDS Interface
The GMCH has a dedicated ANSI/TIA/EIA –644-1995 Specification compliant dual channel LFP
LVDS interface that can support TFT panel resolutions up to SXGA+ with a maximum pixel format of
18 bpp (with SSC supported frequency range from 25-MHz to 112-MHz (single channel/dual channel).
The display pipe selected by the LVDS display port is programmed with the panel timing parameters
that are determined by installed panel specifications or read from an onboard EDID ROM. The
programmed timing values are then “locked” into the registers to prevent unwanted corruption of the
values. From that point on, the display modes are changed by selecting a different source size for that
pipe, programming the VGA registers, or selecting a source size and enabling the VGA. The timing
signals will remain stable and active through mode changes. These mode changes include VGA to
VGA, VGA to HiRes, HiRes to VGA, and HiRes to HiRes.
The transmitter can operate in a variety of modes and supports several data formats. The serializer
supports 6-bit or 8-bit color and single or dual channel operating modes. The display stream from the
display pipe is sent to the LVDS transmitter port at the dot clock frequency, which is determined by the
panel timing requirements. The output of LVDS is running at a fixed multiple of the dot clock
frequency, which is determined by the mode of operation; single or dual channel.
138
Intel^® 852GM/852GMV Chipset GMCH Datasheet