JG82852GMSL7VP Datasheet, PDF (82/176 Pages) Intel Corporation – Intel® 852GM/852GMV Chipset Intel® 852GM/852GMV Chipset Hub (GMCH)

Register Description
R
3.9.11.
CAPPTR – Capabilities Pointer
Address Offset:
Default Value:
Access:
Size:
34h
00h
Read Only
8 bits
The CAPPTR provides the offset that is the pointer to the location of the first device capability in the
capability list.
Bit
7:0
Descriptions
Pointer to the offset of the first capability ID register block: In this case there are no capabilities,
therefore these bits are hardwired to 00h to indicate the end of the capability linked list.
3.9.12.
DRB – DRAM Row Boundary Register - Device #0
Address Offset:
Default Value:
Access:
Size:
40-43h
00h Each
Read/Write
8 bits
The DDR SDRAM Row Boundary Register defines the upper boundary address of each DDR
SDRAM row with a granularity of 32-MB. Each row has its own single-byte DRB register. For
example, a value of 1 in DRB0 indicates that 32-MB of DDR SDRAM has been populated in the first
row. Since Intel 852GM/852GMV GMCH supports a total of 4 rows of System Memory, DRB0-3 are
used. The registers from 44h-4Fh are reserved for DRBs 4-15.
Row0:40h
Row1:41h
Row2:42h
Row3:43h
44h to 4F is reserved.
DRB0 = Total System Memory in row0 (in 32 -MB increments)
DRB1 = Total System Memory in row0 + row1 (in 32 -MB increments)
DRB2 = Total System Memory in row0 + row1 + row2 (in 32 -MB increments)
DRB3 = Total System Memory in row0 + row1 + row2 + row3 (in 32- MB increments)
Each Row is represented by a byte. Each byte has the following format.
Bit
Description
7:0 DDR SDRAM Row Boundary Address: This 8-bit value defines the upper and lower addresses for each DDR
SDRAM row. This 8-bit value is compared against a set of address lines to determine the upper address limit
of a particular row. Also the minimum System Memory supported is 64-MB in 64-Mb granularity; hence bit 0 of
this register must be programmed to a zero.
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Intel^® 852GM/852GMV Chipset GMCH Datasheet