JG82852GMSL7VP Datasheet, PDF (121/176 Pages) Intel Corporation – Intel® 852GM/852GMV Chipset Intel® 852GM/852GMV Chipset Hub (GMCH)

Intel 852GM/852GMV GMCH System Address Map
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4.4.7.1.
Hub Interface Accesses to GMCH that Cross Device Boundaries
Hublink accesses are limited to 256-bytes but have no restrictions on crossing address boundaries. A
single Hublink request may therefore span device boundaries (DDR SDRAM) or cross from valid
addresses to invalid addresses (or vise versa). The GMCH does not support transactions that cross device
boundaries. For reads and for writes requiring completion, the GMCH will provide separate completion
status for each naturally aligned 32 -or 64 -byte block. If the starting address of a transaction hits a valid
address, the portion of a request that hits that target device (DDR SDRAM) will complete normally. The
remaining portion of the access that crosses a device boundary (targets a different device than that of the
starting address) or hits an invalid address will be remapped to System Memory address 0h, snooped on
the host bus, and dispatched to DDR SDRAM. Reads will return all 1’s with Master Abort completion.
Writes will have BE’s deasserted and will terminate with Master Abort if completion is required.
If the starting address of a transaction hits an invalid address the entire transaction will be remapped to
System Memory address 0h, snooped on the host bus, and dispatched to DDR SDRAM. Reads will
return all 1’s with Master Abort completion. Writes will have BE’s deasserted and will terminate with
Master Abort if completion is required.
Intel^® 852GM/852GMV Chipset GMCH Datasheet
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