JG82852GMSL7VP Datasheet, PDF (107/176 Pages) Intel Corporation – Intel® 852GM/852GMV Chipset Intel® 852GM/852GMV Chipset Hub (GMCH)

Register Description
R
3.11.11.
MMADR – Memory Mapped Range Address Register - Device
#2
Address Offset:
Default Value:
Access:
Size:
14 17h
00000000h
Read/Write, Read Only
32 bits
This register requests allocation for the IGD registers and instruction ports. The allocation is for 512-kB
and the base address is defined by bits [31:19].
Bit
31:19
18:4
3
2:1
0
Description
Memory Base Address R/W: Set by the OS, these bits correspond to address signals [31:19].
Address Mask RO: Indicate 512 -kB address range.
Prefetchable Memory RO: Prevents prefetching.
Memory Type RO: Indicates 32-bit address.
Memory / IO Space RO: Indicates System Memory space.
3.11.12.
IOBAR – I/O Base Address Register - (Device #2)
Address offset:
Default:
Access:
Size:
18-1Bh
00000001h
Read/Write
16-bits
This register provides the Base offset of the I/O registers within Device #2. Bits 15:3 are programmable
allowing the I/O Base to be located anywhere in 16-bit I/O Address Space. Bits 2:1 are fixed and return
zero, bit 0 is hardwired to a one indicating that 8-bytes of I/O space are decoded.
Access to the 8Bs of IO space is allowed in PM state D0 when IO Enable (PCICMD bit 0) set. Access is
disallowed in PM states D1-D3 or if IO Enable is clear or if Device #2 is turned off or if internal
graphics is disabled. Note that access to this IO BAR is independent of VGA functionality within Device
#2. Also note that this mechanism is available only through Function #0 of Device#2 and is not
duplicated in Function #1.
If accesses to this IO bar are allowed, then the Intel 852GM/852GMV GMCH claims all 8-bit, 16-bit, or
32-bit IO cycles from the CPU that falls within the 8B claimed.
Bit
31:16
15:3
2:1
0
Description
Reserved
IO Base Address R/W: Set by the OS, these bits correspond to address signals [15:3].
Memory Type RO: Indicates 32-bit address.
Memory / IO Space RO
Intel^® 852GM/852GMV Chipset GMCH Datasheet
107