JG82852GMSL7VP Datasheet, PDF (45/176 Pages) Intel Corporation – Intel® 852GM/852GMV Chipset Intel® 852GM/852GMV Chipset Hub (GMCH)

Register Description
R
3. Register Description
3.1. Conceptual Overview of the Platform Configuration
Structure
The Intel 852GM/852GMV GMCH and ICH4-M are physically connected by Hub Interface A. From a
configuration standpoint, the Hub Interface A is logically PCI bus #0. As a result, all devices internal to
the GMCH and ICH4-M appear to be on PCI bus #0. The system’s primary PCI expansion bus is
physically attached to the ICH4-M and from a configuration perspective, appears to be a hierarchical
PCI bus behind a PCI-to-PCI bridge and therefore has a programmable PCI Bus number. Note that the
primary PCI bus is referred to as PCI_A in this document and is not PCI bus #0 from a configuration
standpoint.
The GMCH contains two PCI devices within a single physical component. The configuration registers
for the two devices are mapped as devices residing on PCI bus #0.
Device #0: Host-Hub Interface Bridge/DDR SDRAM Controller. Logically this appears as a PCI device
residing on PCI bus #0. Physically, Device 0 contains the standard PCI registers, DDR SDRAM
registers, the Graphics Aperture controller, HI control and other GMCH specific registers. Device 0 is
divided into functions as follows:
Function #0: Host Bridge Legacy Registers, including Graphics Aperture control, HI configuration and
Interrupt control registers
Function #1: DDR SDRAM Interface Registers
Function #3: Intel Reserved Registers
Device #2: Integrated Graphics Controller. Logically this appears as a PCI device residing on PCI bus
#0. Physically Device #2 contains the configuration registers for 3D, 2D, and display functions.
Table 12 shows the Device # assignment for the various internal GMCH devices.
Table 12. Device Number Assignment
GMCH Function
Bus #0, Device#
Host-Hl, DDR SDRAM I/f, Legacy control.
Integrated Graphics Controller
Device #0
Device #2
Intel^® 852GM/852GMV Chipset GMCH Datasheet
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