JG82852GMSL7VP Datasheet, PDF (64/176 Pages) Intel Corporation – Intel® 852GM/852GMV Chipset Intel® 852GM/852GMV Chipset Hub (GMCH)

Register Description
R
3.8.16.
DAFC – Device and Function Control Register (Device 0)
Address Offset:
Default Value:
Access:
Size:
54–55h
0000h
Read/Write
16 bits
This 16-bit register controls the visibility of devices and functions within the GMCH to configurations
software.
Bit
15:8
7
6:3
2
1
0
Description
Reserved
Device #2 Disable:
1 = Disabled.
0 = Enabled.
Reserved
Device #0 Function #3 Disable.
1 = Disable Function #3 registers within Device #0 and all associated DDR SDRAM and I/O ranges.
0 = Default is #0, Function #1 within Device #0 is enabled.
Reserved
Device #0 Function #1 Disable:
1 = Disable Function #1 within Device #0.
0 = Default is 0, Function #1 within Device #0 is enabled.
3.8.17.
FDHC – Fixed DRAM Hole Control Register (Device 0)
Address Offset:
Default Value:
Access:
Size:
58h
00h
Read/Write
8 bits
This 8-bit register controls a single fixed DDR SDRAM hole: 15–16 MB.
Bit
7
6:0
Description
Hole Enable (HEN): This field enables a memory hole in DDR SDRAM space. Host cycles matching
an enabled hole are passed on to ICH4-M through Hub Interface. The Intel 852GM/852GMV GMCH
will ignore Hub Interface cycles matching an enabled hole.
NOTE: A selected hole is not re-mapped.
0 = None
1 = 15 MB–16 MB (1MBs)
Reserved
64
Intel^® 852GM/852GMV Chipset GMCH Datasheet