JG82852GMSL7VP Datasheet, PDF (103/176 Pages) Intel Corporation – Intel® 852GM/852GMV Chipset Intel® 852GM/852GMV Chipset Hub (GMCH)

Register Description
R
3.11.3.
PCICMD2 – PCI Command Register - Device #2
Address Offset:
Default:
Access:
Size:
04h 05h
0000h
Read Only, Read/Write
16 bits
This 16-bit register provides basic control over the IGD’s ability to respond to PCI cycles. The PCICMD
Register in the IGD disables the IGD PCI compliant master accesses to main System Memory.
Bit
15:10
9
8
7
6
5
4
3
2
1
0
Description
Reserved
Fast Back-to-Back (FB2B) RO.
SERR# Enable (SERRE) RO.
Address/Data Stepping RO.
Parity Error Enable (PERRE) RO.
Video Palette Snooping (VPS) RO.
Memory Write and Invalidate Enable (MWIE) RO.
Special Cycle Enable (SCE) RO.
Bus Master Enable (BME) R/W: This bit determines if the IGD is to function as a PCI compliant master.
0= Disable IGD bus mastering (default).
1 = Enable IGD bus mastering.
Memory Access Enable (MAE)
accesses.
0= Disable (default).
1 = Enable.
R/W: This bit controls the IGD’s response to System Memory space
I/O Access Enable (IOAE)
0 = Disable (default).
1 = Enable.
R/W: This bit controls the IGD’s response to I/O space accesses.
Intel^® 852GM/852GMV Chipset GMCH Datasheet
103