JG82852GMSL7VP Datasheet, PDF (109/176 Pages) Intel Corporation – Intel® 852GM/852GMV Chipset Intel® 852GM/852GMV Chipset Hub (GMCH)

Register Description
R
3.11.16.
INTRLINE Interrupt Line Register - Device #2
Address Offset:
Default Value:
Access:
Size:
3Ch
00h
Read/Write
8 bits
Bit
7:0
Description
Interrupt Connection: Used to communicate interrupt line routing information. POST software writes the
routing information into this register as it initializes and configures the system. The value in this register
indicates which input of the system interrupt controller that the device’s interrupt pin is connected to.
3.11.17.
INTRPIN Interrupt Pin Register - Device #2
Address Offset:
Default Value:
Access:
Size:
3Dh
01h, 00h for Function #1
Read Only
8 bits
Bit
7:0
Description
Interrupt Pin: As a single function device, the IGD (Integrated GFX Device) specifies INTA# as its interrupt
pin. 01h=INTA#. For Function #1, this register is set to 00h.
3.11.18.
MINGNT – Minimum Grant Register - Device #2
Address Offset:
Default Value:
Access:
Size:
3Eh
00h
Read Only
8 bits
Bit
Description
7:0 Minimum Grant Value: The IGD does not burst as a PCI compliant master.
3.11.19.
MAXLAT – Maximum Latency Register - Device #2
Address Offset:
Default Value:
Access:
Size:
3Fh
00h
Read Only
8 bits
Bit
Description
7:0 Maximum Latency Value: Bits[7:0]=00h. The IGD has no specific requirements for how often it needs to
access the PCI bus.
Intel^® 852GM/852GMV Chipset GMCH Datasheet
109