JG82852GMSL7VP Datasheet, PDF (117/176 Pages) Intel Corporation – Intel® 852GM/852GMV Chipset Intel® 852GM/852GMV Chipset Hub (GMCH)

Intel 852GM/852GMV GMCH System Address Map
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4.4.2.1.
4.4.2.2.
4.4.2.3.
4.4.2.4.
4.4.2.5.
Extended SMRAM Address Range (HSEG and TSEG)
The HSEG and TSEG SMM transaction address spaces reside in this extended System Memory area.
HSEG
SMM mode CPU accesses to enabled HSEG are remapped to 000A0000h-000BFFFFh. Non-SMM
mode CPU accesses to enabled HSEG are considered invalid are terminated immediately on the FSB.
The exceptions to this rule are Non-SMM mode Write Back cycles that are remapped to SMM space to
maintain cache coherency. Hub Interface originated cycles to enabled SMM space are not allowed.
Physical DDR SDRAM behind the HSEG transaction address is not remapped and is not accessible.
TSEG
TSEG is 1-MB in size and is at the top of physical System Memory. SMM mode CPU accesses to
enabled TSEG access the physical DDR SDRAM at the same address. Non-SMM mode CPU accesses
to enabled TSEG are considered invalid and are terminated immediately on the FSB. The exceptions to
this rule are Non-SMM-mode Write Back cycles that are directed to the physical SMM space to maintain
cache coherency. Hub Interface originated cycles that enable SMM space are not allowed.
The size of the SMRAM space is determined by the USMM value in the SMRAM register. When the
extended SMRAM space is enabled, non-SMM CPU accesses and all other accesses in this range are
forwarded to the Hub Interface. When SMM is enabled the amount of System Memory available to the
system is equal to the amount of physical DDR SDRAM minus the value in the TSEG register.
Intel Dynamic Video Memory Technology (DVMT)
The IGD supports DVMT in a non-graphics System Memory configuration. DVMT is a mechanism that
manages System Memory and the internal graphics device for optimal graphics performance. DVMT-
enabled software drivers, working with the memory arbiter and the operating system, utilize the System
Memory to support 2D graphics and 3D applications. DVMT dynamically responds to application
requirements by allocating the proper amount of display and texturing memory.
PCI Memory Address Range (Top of Main System Memory to 4 GB)
The address range from the top of main DDR SDRAM to 4-GB (top of physical System Memory space
supported by the GMCH) is normally mapped via the Hub Interface to PCI.
As an internal graphics configuration, there are two exceptions to this rule.
1. The first exception is addresses decoded to the Graphics Memory Range. One per function in
device #2.
2. The second exception is addresses decoded to the System Memory Mapped Range of the Internal
Graphics Device. One per function in device #2. Both exception cases are forwarded to the
Internal Graphics Device.
There are two sub-ranges within the PCI Memory address range defined as APIC Configuration Space
and High BIOS Address Range. As an Internal Graphics Device, the Graphics Memory Range and the
Memory Mapped Range of the Internal Graphics Device MUST NOT overlap with these two ranges.
These ranges are described in detail in the following paragraphs.
Intel^® 852GM/852GMV Chipset GMCH Datasheet
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