JG82852GMSL7VP Datasheet, PDF (70/176 Pages) Intel Corporation – Intel® 852GM/852GMV Chipset Intel® 852GM/852GMV Chipset Hub (GMCH)

Register Description
R
3.8.20.
ESMRAMC – Extended System Management RAM Control
(Device 0)
Address Offset:
Default Value:
Access:
Size:
61h
38h
Read/Write
8 bits
The Extended SMRAM register controls the configuration of Extended SMRAM space. The Extended
SMRAM (E_SMRAM) memory provides a write-back cacheable SMRAM memory space that is above
1 MB.
Bit
7
6
5
4
3
2:1
0
Description
H_SMRAM_EN (H_SMRAME): Controls the SMM memory space location (i.e., above 1 MB or below 1
MB). When G_SMRAME is 1 and H_SMRAME this bit is set to 1, the high SMRAM memory space is
enabled. SMRAM accesses from 0FEDA0000h to 0FEDBFFFFh are remapped to DDR SDRAM address
000A0000h to 000BFFFFh.
Once D_LCK is set, this bit becomes read only.
E_SMRAM_ERR (E_SMERR): This bit is set when CPU accesses the defined DDR SDRAM ranges in
Extended SMRAM (High System Memory and T-segment) while not in SMM space. It is software’s
responsibility to clear this bit. The software must write a 1 to this bit to clear it.
SMRAM_Cache (SM_CACHE): Intel 852GM/852GMV GMCH forces this bit to 1.
SMRAM_L1_EN (SM_L1): Intel 852GM/852GMV GMCH forces this bit to 1.
SMRAM_L2_EN (SM_L2): Intel 852GM/852GMV GMCH forces this bit to 1.
Reserved
TSEG_EN (T_EN): Enabling of SMRAM memory (TSEG, 1 Mbytes of additional SMRAM memory) for
Extended SMRAM space only. When G_SMRAME =1 and TSEG_EN = 1, the TSEG is enabled to appear
in the appropriate physical address space.
Once D_LCK is set, this bit becomes read only.
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Intel^® 852GM/852GMV Chipset GMCH Datasheet