JG82852GMSL7VP Datasheet, PDF (3/176 Pages) Intel Corporation – Intel® 852GM/852GMV Chipset Intel® 852GM/852GMV Chipset Hub (GMCH)

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Contents
1.
Introduction .................................................................................................................................19
1.1. Terminology ...................................................................................................................19
1.2. Reference Documents ...................................................................................................20
1.3. System Architecture Overview.......................................................................................21
1.3.1. Intel 852GM GMCH System Architecture.........................................................21
1.3.2. Intel 852GMV GMCH System Architecture ......................................................21
1.4. Processor Host Interface ...............................................................................................23
1.4.1. Intel 852GM GMCH Processor Host Interface .................................................23
1.4.2. Intel 852GMV GMCH Processor Host Interface...............................................24
1.5. Intel 852GM/852GMV GMCH Host Bus Error Checking ...............................................24
1.6. Intel 852GM/852GMV GMCH System Memory Interface..............................................24
1.7. Intel 852GM/852GMV GMCH Internal Graphics ...........................................................25
1.7.1. Intel 852GM/852GMV GMCH Analog Display Port ..........................................25
1.7.2. Intel 852GM/852GMV GMCH Integrated LVDS Port .......................................25
1.7.3. Intel 852GM/852GMV GMCH Integrated DVO Port .........................................26
1.8. Hub Interface .................................................................................................................26
1.9. Address Decode Policies ...............................................................................................26
1.10. Intel 852GM/852GMV GMCH Clocking .........................................................................26
1.11. System Interrupts...........................................................................................................27
2.
Signal Description.......................................................................................................................29
2.1. Host Interface Signals....................................................................................................30
2.2. DDR SDRAM Interface ..................................................................................................33
2.3. Hub Interface Signals.....................................................................................................34
2.4. Clocks ............................................................................................................................35
2.5. Internal Graphics Display Signals..................................................................................37
2.5.1.
2.5.2.
2.5.3.
2.5.4.
Dedicated LFP LVDS Interface ........................................................................37
Digital Video Port C (DVOC) ............................................................................38
Analog Display..................................................................................................39
General Purpose Input/Output Signals.............................................................40
2.6. Voltage References, PLL Power....................................................................................42
3.
Register Description ...................................................................................................................45
3.1. Conceptual Overview of the Platform Configuration Structure ......................................45
3.2. Nomenclature for Access Attributes ..............................................................................46
3.3. Standard PCI Bus Configuration Mechanism ................................................................47
3.4. Routing Configuration Accesses....................................................................................47
3.4.1. PCI Bus #0 Configuration Mechanism .............................................................47
3.4.2. Primary PCI and Downstream Configuration Mechanism................................47
3.5. Register Definitions........................................................................................................48
3.6. I/O Mapped Registers ....................................................................................................49
3.6.1. CONFIG_ADDRESS – Configuration Address Register..................................49
3.6.2. CONFIG_DATA – Configuration Data Register ...............................................51
3.7. VGA I/O Mapped Registers ...........................................................................................52
3.8. Intel 852GM/852GMV GMCH Host-Hub Interface Bridge Device Registers
(Device #0, Function #0) ...............................................................................................53
3.8.1. VID – Vendor Identification...............................................................................54
3.8.2. DID – Device Identification ...............................................................................54
Intel^® 852GM/852GMV Chipset GMCH Datasheet
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