JG82852GMSL7VP Datasheet, PDF (100/176 Pages) Intel Corporation – Intel® 852GM/852GMV Chipset Intel® 852GM/852GMV Chipset Hub (GMCH)

Register Description
R
3.10.11.
CAPPTR – Capabilities Pointer
Address Offset:
Default Value:
Access:
Size:
34h
00h
Read Only
8 bits
The CAPPTR provides the offset that is the pointer to the location of the first device capability in the
capability list.
Bit
Descriptions
7:0
Pointer to the offset of the first capability ID register block: In this case there are no capabilities
therefore these bits are hardwired to 00h to indicate the end of the capability-linked list.
3.10.12.
HPLLCC – HPLL Clock Control Register (Device 0)
Address Offset:
Default Value:
Access:
Size:
C0–C1h
00h
Read Only
16 bits
Bit
15:11
10
9
8
7:2
1:0
Descriptions
Reserved
HPLL VCO Change Sequence Initiate Bit:
Software must write a '0' to clear this bit and then write a '1' to initiate sequence again.
Hphase Reset Bit:
1 = Assert
0 = Deassert (default)
Reserved
Reserved
HPLL Clock Control:
Software is allowed to update this register.
See Table 21 for Clock definitions.
Table 21. Intel 852GM/852GMV GMCH Configurations
Straps Read Through
HPLLCC[1:0]: D0:F3:Register
Offset C0-C1h, bits[1:0]
FSB Frequency
System Memory
Frequency
00
400 MHz
266 MHz
10
400 MHz
200 MHz
GFX Core
Clock(Low)
133 MHz
133 MHz
GFX Core
Clock (High)
133 MHz
133 MHz
100
Intel^® 852GM/852GMV Chipset GMCH Datasheet