JG82852GMSL7VP Datasheet, PDF (47/176 Pages) Intel Corporation – Intel® 852GM/852GMV Chipset Intel® 852GM/852GMV Chipset Hub (GMCH)

Register Description
R
3.3.
3.4.
3.4.1.
3.4.2.
Standard PCI Bus Configuration Mechanism
The PCI Bus defines a slot based “configuration space” that allows each device to contain up to eight
functions with each function containing up to 256, 8-bit configuration registers. The PCI specification
defines two bus cycles to access the PCI configuration space: Configuration Read and Configuration
Write. Memory and I/O spaces are supported directly by the CPU. Configuration space is supported by
a mapping mechanism implemented within the GMCH. The PCI 2.2 specification defines two
mechanisms to access configuration space, Mechanism #1 and Mechanism #2. The GMCH supports
only Mechanism #1.
The configuration access mechanism makes use of the CONFIG_ADDRESS Register (at I/O address
0CF8h though 0CFBh) and CONFIG_DATA Register (at I/O address 0CFCh though 0CFFh). To
reference a configuration register a Dword I/O write cycle is used to place a value into
CONFIG_ADDRESS that specifies the PCI bus, the device on that bus, the function within the device,
and a specific configuration register of the device function being accessed. CONFIG_ADDRESS[31]
must be 1 to enable a configuration cycle. CONFIG_DATA then becomes a window into the four bytes
of configuration space specified by the contents of CONFIG_ADDRESS. Any read or write to
CONFIG_DATA will result in the GMCH translating the CONFIG_ADDRESS into the appropriate
configuration cycle.
The GMCH is responsible for translating and routing the CPU’s I/O accesses to the
CONFIG_ADDRESS and CONFIG_DATA registers to internal GMCH configuration registers and Hub
Interface.
Routing Configuration Accesses
The GMCH supports one bus interface: the Hub Interface. PCI configuration cycles are selectively
routed to this interface. The GMCH is responsible for routing PCI configuration cycles to the proper
interface. PCI configuration cycles to the ICH4-M internal devices, and Primary PCI (including
downstream devices) are routed to the ICH4-M via the Hub Interface. A detailed description of the
mechanism for translating CPU I/O bus cycles to configuration cycles on one of the buses is described in
the following section.
PCI Bus #0 Configuration Mechanism
The GMCH decodes the Bus Number (bits 23:16) and the Device Number fields of the
CONFIG_ADDRESS register. If the Bus Number field of CONFIG_ADDRESS is 0 the configuration
cycle is targeting a PCI Bus #0 device.
The Host-Hub Interface Bridge entity within the GMCH is hardwired as Device #0 on PCI Bus #0.
Configuration cycles to any of the GMCH’s internal devices are confined to the GMCH and not sent
over Hub Interface. Accesses to disabled GMCH internal devices will be forwarded over the Hub
Interface as Type 0 Configuration Cycles.
Primary PCI and Downstream Configuration Mechanism
The ICH4-M compares the non-zero Bus Number with the SECONDARY BUS NUMBER and
SUBORDINATE BUS NUMBER registers of its P2P bridges to determine if the configuration cycle is
meant for Primary PCI or a downstream PCI bus.
Intel^® 852GM/852GMV Chipset GMCH Datasheet
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