JG82852GMSL7VP Datasheet, PDF (148/176 Pages) Intel Corporation – Intel® 852GM/852GMV Chipset Intel® 852GM/852GMV Chipset Hub (GMCH)

Testability
R
Figure 9. XOR Chain Test Mode Entry Events Diagram
powerok
VSYNC
HSYNC
LCLKCTLA
RSTIN# (PCI reset)
Don't care
Don't care
Don't care
Note: HSYNC and LCLKCTLA = XOR Chain Test Mode Activation; No clock is required for XOR Chain
Test Mode. A minimum of 50 ns PWROK assertion prior to RSTIN# assertion is recommended. A
minimum of 10 ns VSYNC/HSYNC/LCLKCTLA assertion prior to PWROK assertion is recommended.
Please refer to ALLZ Test Mode Entry Events Diagram in Figure 10.
Figure 10. ALLZ Test Mode Entry Events Diagram
powerok
VSYNC
HSYNC
LCLKCTLA
RSTIN# (PCI reset)
Don't care
Don't care
Don't care
NOTE: VSYNC and LCLKCTLA = ALL Z Test Mode Activation; No clock is required for ALLZ Test Mode Activation.
A minimum of 50 ns PWROK assertion prior to RSTIN# assertion is recommended. A minimum of 10 ns
VSYNC/HSYNC/LCLKCTLA assertion prior to PWROK assertion is recommended.
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Intel^® 852GM/852GMV Chipset GMCH Datasheet