JG82852GMSL7VP Datasheet, PDF (5/176 Pages) Intel Corporation – Intel® 852GM/852GMV Chipset Intel® 852GM/852GMV Chipset Hub (GMCH)

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3.11.
3.10.11.CAPPTR – Capabilities Pointer ......................................................................100
3.10.12.HPLLCC – HPLL Clock Control Register (Device 0)......................................100
Intel 852GM/852GMV GMCH Integrated Graphics Device Registers (Device #2,
Function #0).................................................................................................................101
3.11.1. VID2 – Vendor Identification Register – Device #2 ........................................102
3.11.2. DID2 – Device Identification Register - Device #2 .........................................102
3.11.3. PCICMD2 – PCI Command Register - Device #2 ..........................................103
3.11.4. PCISTS2 – PCI Status Register - Device #2..................................................104
3.11.5. RID2 – Revision Identification Register - Device #2.......................................104
3.11.6. CC – Class Code Register - Device #2 ..........................................................105
3.11.7. CLS – Cache Line Size Register - Device #2.................................................105
3.11.8. MLT2 – Master Latency Timer Register - Device #2......................................105
3.11.9. HDR2 – Header Type Register - Device #2 ...................................................106
3.11.10.GMADR – Graphics Memory Range Address Register - Device #2 ..............106
3.11.11.MMADR – Memory Mapped Range Address Register - Device #2 ...............107
3.11.12.IOBAR – I/O Base Address Register - (Device #2) ........................................107
3.11.13.SVID2 – Subsystem Vendor Identification Register - Device #2....................108
3.11.14.SID2 – Subsystem Identification Register - Device #2...................................108
3.11.15.ROMADR – Video BIOS ROM Base Address Registers - Device #2 ............108
3.11.16.INTRLINE Interrupt Line Register - Device #2.............................................109
3.11.17.INTRPIN Interrupt Pin Register - Device #2 ................................................109
3.11.18.MINGNT – Minimum Grant Register - Device #2 ...........................................109
3.11.19.MAXLAT – Maximum Latency Register - Device #2 ......................................109
3.11.20.PMCAP – Power Management Capabilities Register - Device #2 .................110
3.11.21.PMCS – Power Management Control/Status Register - Device #2 ...............110
4.
Intel 852GM/852GMV GMCH System Address Map ...............................................................111
4.1. System Memory Address Ranges ...............................................................................111
4.2. Compatibility Area........................................................................................................113
4.3. Extended System Memory Area ..................................................................................115
4.4. Main System Memory Address Range (0010_0000h to Top of Main Memory) ..........116
4.4.1.
4.4.2.
4.4.3.
4.4.4.
4.4.5.
4.4.6.
4.4.7.
15 MB-16 MB Window....................................................................................116
Pre-allocated System Memory .......................................................................116
4.4.2.1. Extended SMRAM Address Range (HSEG and TSEG) ...............117
4.4.2.2. HSEG ............................................................................................117
4.4.2.3. TSEG.............................................................................................117
4.4.2.4. Intel Dynamic Video Memory Technology (DVMT).......................117
4.4.2.5. PCI Memory Address Range (Top of Main System Memory
to 4 GB) .........................................................................................117
4.4.2.6. APIC Configuration Space (FEC0_0000h -FECF_FFFFh,
FEE0_0000h- FEEF_FFFFh)........................................................118
4.4.2.7. High BIOS Area (FFE0_0000h -FFFF_FFFFh) ............................118
System Management Mode (SMM) Memory Range ......................................118
4.4.3.1. SMM Space Restrictions...............................................................119
4.4.3.2. SMM Space Definition...................................................................119
System Memory Shadowing...........................................................................119
I/O Address Space .........................................................................................119
GMCH Decode Rules and Cross-Bridge Address Mapping...........................120
Hub Interface Decode Rules ..........................................................................120
4.4.7.1. Hub Interface Accesses to GMCH that Cross Device
Boundaries ....................................................................................121
Intel^® 852GM/852GMV Chipset GMCH Datasheet
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