JG82852GMSL7VP Datasheet, PDF (91/176 Pages) Intel Corporation – Intel® 852GM/852GMV Chipset Intel® 852GM/852GMV Chipset Hub (GMCH)

Register Description
R
Bit
31:28
27:24
Description
DDR SDRAM Throttle Mode (TMODE):
Four bits control which mechanisms for throttling are enabled in an “OR” fashion. Counter-based
throttling is lower priority than thermal trips throttling when both are enabled and tripped. Counter-based
trips point throttling values and Thermal-based trip point throttling values are specified in this register.
If the counter and thermal mechanisms for either rank or Intel 852GM/852GMV GMCH are both enabled,
throttle settings for the one that trips first is used until the end of the second gdsw.
[Rank Counter, Intel 852GM/852GMV GMCH Write Counter, Rank Thermal Sensor, Intel
852GM/852GMV GMCH Thermal Sensor]
0000 = Throttling turned off. This is the default setting. All Counters are off.
0001 = Only Intel 852GM/852GMV GMCH Thermal Sensor based throttling is enabled. If Intel
852GM/852GMV GMCH thermal sensor is tripped, write throttling begins based on the setting in WTTC.
0010 = Only Rank Thermal Sensor based throttling enabled. When the external SO-DIMM thermal
sensor is tripped DDR SDRAM throttling begins based on the setting in RTTC.
0011 = Both Rank and Intel 852GM/852GMV GMCH Thermal Sensor based throttling enabled. When
the external SO-DIMM thermal sensor is tripped DDR SDRAM throttling begins based on the setting in
RTTC. If the Intel 852GM/852GMV GMCH thermal sensor is tripped, write throttling begins based on the
setting in WTTC.
0100 = Only the Intel 852GM/852GMV GMCH Write Counter mechanism is enabled. When the
threshold set in the GDT field is reached, DDR SDRAM throttling begins based on the setting in WCTC.
0101 = Intel 852GM/852GMV GMCH Thermal Sensor and Intel 852GM/852GMV GMCH Write DDR
SDRAM Counter mechanisms are both enabled. If the Intel 852GM/852GMV GMCH write DDR
SDRAM counter mechanism threshold is reached, DDR SDRAM throttling begins based on the setting in
WCTC. If the Intel 852GM/852GMV GMCH thermal sensor is tripped, DDR SDRAM throttling begins
based on the setting in WTTC. If both threshold mechanisms are tripped, the DDR SDRAM throttling
begins based on the settings in WTTC.
0110 = Rank Thermal Sensor and Intel 852GM/852GMV GMCH Write DDR SDRAM Counter
mechanisms are both enabled. If the Intel 852GM/852GMV GMCH write DDR SDRAM counter
mechanism threshold is reached, DDR SDRAM throttling begins based on setting in WCTC. If the
external SO-DIMM thermal sensor is tripped, Rank DRAM throttling begins based on the setting in
RTTC.
0111 = Similar to 0101 for writes and when the Rank thermal sensor is tripped DDR SDRAM throttling
begins based on the setting in RTTC.
1000 = Only Rank Counter mechanism is enabled. When the threshold set in the GDT field is reached,
DDR SDRAM throttling begins based on the setting in RCTC.
1001 = Rank Counter mechanism is enabled and Intel 852GM/852GMV GMCH Thermal Sensor
based throttling are both enabled. If Intel 852GM/852GMV GMCH thermal sensor is tripped, write
throttling begins based on the setting in WTTC. When the threshold set in the GDT field is reached, DDR
SDRAM throttling begins based on the setting in RCTC.
1010 = Rank thermal Sensor and Rank DDR SDRAM Counter mechanisms are both enabled. If the
rank DDR SDRAM counter mechanism threshold is reached, DDR SDRAM throttling begins based on
the setting in RCTC. If the external SO-DIMM thermal sensor is tripped, DRAM throttling begins based
on the setting in RTTC.
1011 = Similar to 1010 and If the Intel 852GM/852GMV GMCH thermal sensor is tripped, write
throttling begins based on the setting in WTTC.
1111 = Rank and Intel 852GM/852GMV GMCH Thermal Sensor based throttling and Rank and Intel
852GM/852GMV GMCH Write Counter based throttling are enabled. If both the write counter and Intel
852GM/852GMV GMCH thermal sensor based mechanisms are tripped, DDR SDRAM throttling begins
based on the setting allowed in WTTC. If both the rank counter and rank thermal sensor based
mechanisms are tripped, DDR SDRAM throttling begins based on the setting allowed in RTTC.
Read Counter Based Power Throttle Control (RCTC): These bits select the Counter based Power
Throttle Bandwidth Limits for Read operations to System Memory.
Intel^® 852GM/852GMV Chipset GMCH Datasheet
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