JG82852GMSL7VP Datasheet, PDF (120/176 Pages) Intel Corporation – Intel® 852GM/852GMV Chipset Intel® 852GM/852GMV Chipset Hub (GMCH)

Intel 852GM/852GMV GMCH System Address Map
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the host bridge the GMCH contains two internal registers in the CPU I/O space, Configuration Address
Register (CONFIG_ADDRESS) and the Configuration Data Register (CONFIG_DATA). These
locations are used to implement configuration space access mechanism and as described in the
Configuration register section.
The CPU allows 64kB +3B to be addressed within the I/O space. The GMCH propagates the CPU I/O
address without any translation on to the destination bus and therefore provides addressability for 64 k+3
byte locations. Note that the upper 3 locations can be accessed only during I/O address wrap-around
when CPU bus A16# address signal is asserted. A16# is asserted on the CPU bus whenever an I/O
access is made to 4 bytes from address 0FFFDh, 0FFFEh, or 0FFFFh. A16# is also asserted when an I/O
access is made to 2 bytes from address 0FFFFh.
A set of I/O accesses (other than ones used for configuration space access) is consumed by the internal
graphics device if it is enabled. The mechanisms for internal graphics IO decode and the associated
control is explained later.
The I/O accesses (other than ones used for configuration space access) are forwarded normally to the
Hub Interface. The GMCH will not post I/O write cycles to IDE.
4.4.6.
GMCH Decode Rules and Cross-Bridge Address Mapping
The address map described above applies globally to accesses arriving on any of the three interfaces i.e.
Host bus, IGD, and Hub Interface.
4.4.7.
Hub Interface Decode Rules
The GMCH accepts accesses from Hub Interface to the following address ranges:
All memory read and write accesses to Main DDR SDRAM including PAM region (except SMM
space)
All memory read/write accesses to the Graphics Aperture (DRAM) defined by APBASE and
APSIZE.
Memory writes to VGA range.
All memory reads from the Hub Interface A that are targeted > 4-GB System Memory range will be
terminated with Master Abort completion, and all memory writes (>4-GB) from the Hub Interface will
be ignored.
Hub Interface System Memory accesses that fall elsewhere within the System Memory range are
considered invalid and will be remapped to System Memory address 0h, snooped on the host bus, and
dispatched to DDR SDRAM. Reads will return all 1’s with Master Abort completion. Writes will have
BE’s deasserted and will terminate with Master Abort if completion is required. I/O cycles will not be
accepted. They are terminated with Master Abort completion packets.
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Intel^® 852GM/852GMV Chipset GMCH Datasheet