JG82852GMSL7VP Datasheet, PDF (34/176 Pages) Intel Corporation – Intel® 852GM/852GMV Chipset Intel® 852GM/852GMV Chipset Hub (GMCH)

Signal Description
R
Signal Name
SMAB[5,4,2,1]
SDM[8:0]
RCVENOUT#
RCVENIN#
Type
O
SSTL_2
O
SSTL_2
O
SSTL_2
O
SSTL_2
Description
Memory Address Copies: These signals are identical to SMA[5,4,2,1] and are used
to reduce loading for selective CPC(clock-per-command). These copies are not
inverted.
Data Mask: When activated during writes, the corresponding data groups in the
DDR SDRAM are masked. There is one SDM for every eight data lines. SDM can be
sampled on both edges of the data strobes.
NOTE: ECC error detection is NOT supported: SDM[8] signal should be left as NC
(“No Connect”) on the Intel 852GM/852GMV GMCH.
Clock Output: Used to emulate source-synch clocking for reads. This pin is a NC.
Clock Input: Used to emulate source-synch clocking for reads. This is pin is a NC.
2.3. Hub Interface Signals
Table 5. Hub Interface Signals
Signal Name
Type
HL[10:0]
I/O
1.5
HLSTB
I/O
1.5
HLSTB#
I/O
1.5
Description
Packet Data: Data signals used for HI read and write operations.
Packet Strobe: One of two differential strobe signals used to transmit or receive
packet data over HI.
Packet Strobe Complement: One of two differential strobe signals used to transmit
or receive packet data over HI.
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Intel^® 852GM/852GMV Chipset GMCH Datasheet