JG82852GMSL7VP Datasheet, PDF (84/176 Pages) Intel Corporation – Intel® 852GM/852GMV Chipset Intel® 852GM/852GMV Chipset Hub (GMCH)

Register Description
R
3.9.14.
DRT – DRAM Timing Register - Device #0
Address Offset:
Default Value:
Access:
Size:
60-63h
18004425h
Read/Write
32 bits
This register controls the timing of the DDR SDRAM Controller.
Bit
Description
31
30
29:28
DDR Internal Write to Read Command delay (tWTR):
The tWTR is a std. DDR SDRAM timing parameter with a value of 1 CK for CL=2 and 2.5. The tWTR is used
to time RD command after a WR command (to same row):
‘0’: tWTR is set to 1 Clock (CK), used for DDR SDRAM CL=2 or 2.5
‘1’: Reserved
DDR Write Recovery time (tWR):
Write recovery time is a std. DDR timing parameter with the value of 15 ns. It should be set to 2 CK when
DDR200 is used. The tWR is used to time PRE command launch after a WR command, when DDR SDRAM
components are populated.
‘0’: tWR is set to 2 Clocks (CK)
‘1’: tWR is set to 3 Clocks (CK)
Back To Back Write-Read commands spacing (DDR different rows/bank):
This field determines the WR-RD command spacing, in terms of common clocks for DDR SDRAM based on
the following formula: DQSS + 0.5xBL + TA (wr-rd) – CL
DQSS: is time from write command to data and is always 1 CK
BL: is burst length and can be set to 4.
TA (wr-rd): is required DQ turn-around, can be set to 1 or 2 CK
CL: is CAS latency, can be set to 2 or 2.5
Examples of usage:
For BL=4, with single DQ turn-around and CL=2, this field must be set to 2 CK (1+2+1-2)
Encoding CK between WR and RD commands
BL=4
00:
4
01:
3
10:
2
11:
Reserved
84
Intel^® 852GM/852GMV Chipset GMCH Datasheet