JG82852GMSL7VP Datasheet, PDF (118/176 Pages) Intel Corporation – Intel® 852GM/852GMV Chipset Intel® 852GM/852GMV Chipset Hub (GMCH)

Intel 852GM/852GMV GMCH System Address Map
4.4.2.6.
4.4.2.7.
R
APIC Configuration Space (FEC0_0000h -FECF_FFFFh, FEE0_0000h-
FEEF_FFFFh)
This range is reserved for APIC configuration space that includes the default I/O APIC configuration
space. The default Local APIC configuration space is FEE0_0000h to FEEF_0FFFh.
CPU accesses to the Local APIC configuration space do not result in external bus activity since the
Local APIC configuration space is internal to the CPU. However, an MTRR must be programmed to
make the Local APIC range uncacheable (UC). The Local APIC base address in each CPU should be
relocated to the FEC0_0000h (4 GB-20 MB) to FECF_FFFFh range so that one MTRR can be
programmed to 64-kB for the Local and I/O APICs. The I/O APIC(s) usually resides in the ICH4-M
portion of the chip-set or as a stand-alone component(s).
I/O APIC units will be located beginning at the default address FEC0_0000h. The first I/O APIC will be
located at FEC0_0000h. Each I/O APIC unit is located at FEC0_x000h where x is I/O APIC unit number
0 through F(hex). This address range will be normally mapped to Hub Interface.
The address range between the APIC configuration space and the High BIOS (FED0_0000h to
FFDF_FFFFh) is always mapped to the Hub Interface.
High BIOS Area (FFE0_0000h -FFFF_FFFFh)
The top 2-MB of the Extended Memory Region is reserved for System BIOS (High BIOS), extended
BIOS for PCI devices, and the A20 alias of the system BIOS. CPU begins execution from the High
BIOS after reset. This region is mapped to Hub Interface so that the upper subset of this region aliases to
16 MB to 256-kB range. The actual address space required for the BIOS is less than 2 MB but the
minimum CPU MTRR range for this region is 2-MB so that full 2-MB must be considered.
4.4.3. System Management Mode (SMM) Memory Range
The GMCH supports the use of main System Memory as System Management RAM (SMM RAM)
enabling the use of System Management Mode. The GMCH supports three SMM options: Compatible
SMRAM (C_SMRAM), High Segment (HSEG), and Top of Memory Segment (TSEG). System
Management RAM space provides a System Memory area that is available for the SMI handler’s and
code and data storage. This System Memory resource is normally hidden from the system OS so that the
processor has immediate access to this System Memory space upon entry to SMM. The GMCH provides
three SMRAM options:
Below 1 -MByte option that supports compatible SMI handlers.
Above 1 -MByte option that allows new SMI handlers to execute with write-back cacheable SMRAM.
Above 1-MByte solutions require changes to compatible SMRAM handlers code to properly execute
above 1-MByte.
Note: Hub Interface is not allowed to access the SMM space.
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Intel^® 852GM/852GMV Chipset GMCH Datasheet