JG82852GMSL7VP Datasheet, PDF (119/176 Pages) Intel Corporation – Intel® 852GM/852GMV Chipset Intel® 852GM/852GMV Chipset Hub (GMCH)

Intel 852GM/852GMV GMCH System Address Map
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4.4.3.1.
SMM Space Restrictions
If any of the following conditions are violated the results of SMM accesses are unpredictable and may
cause the system to hang:
1. The Compatible SMM space must not be set-up as cacheable.
2. High or TSEG SMM transaction address space must not overlap address space assigned to DDR
SDRAM or to any “PCI” devices (including Hub Interface and graphics devices). This is a BIOS
responsibility.
3. Both D_OPEN and D_CLOSE must not be set to 1 at the same time.
4. When TSEG SMM space is enabled, the TSEG space must not be reported to the OS as available
. This is a BIOS responsibility.
4.4.3.2. SMM Space Definition
SMM space is defined by its addressed SMM space and its DDR SDRAM SMM space. The addressed
SMM space is defined as the range of bus addresses used by the CPU to access SMM space. DDR
SDRAM SMM space is defined as the range of physical DDR SDRAM locations containing the SMM
code. SMM space can be accessed at one of three transaction address ranges: Compatible, High, and
TSEG. The Compatible and TSEG SMM space is not remapped and therefore the addressed and DDR
SDRAM SMM space is the same address range. Since the High SMM space is remapped the addressed
and DDR SDRAM SMM space is a different address range. Note that the High DDR SDRAM space is
the same as the Compatible Transaction Address space. The table below describes three unique address
ranges:
1. Compatible Transaction Address (Adr C)
2. High Transaction Address (Adr H)
3. TSEG Transaction Address (Adr T)
These abbreviations are used later in Table 25.
Table 25. SMM Space Transaction Handling
SMM Space Enabled
Transaction Address Space (Adr)
DRAM Space (DRAM)
Compatible (C)
High (H)
TSEG (T)
A0000h to BFFFFh
0FEDA0000h to 0FEDBFFFFh
(TOM-TSEG_SZ) to TOM
A0000h to BFFFFh
A0000h to BFFFFh
(TOM-TSEG_SZ) to TOM
4.4.4.
4.4.5.
System Memory Shadowing
Any block of System Memory that can be designated as read-only or write-only can be “shadowed” into
GMCH DDR SDRAM. Typically this is done to allow ROM code to execute more rapidly out of main
DDR SDRAM. ROM is used as a read-only during the copy process while DDR SDRAM at the same
time is designated write-only. After copying, the DDR SDRAM is designated read-only so that ROM is
shadowed. CPU bus transactions are routed accordingly.
I/O Address Space
The GMCH does not support the existence of any other I/O devices beside itself on the CPU bus. The
GMCH generates Hub Interface or PCI bus cycles for all CPU I/O accesses that it does not claim. Within
Intel^® 852GM/852GMV Chipset GMCH Datasheet
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