JG82852GMSL7VP Datasheet, PDF (29/176 Pages) Intel Corporation – Intel® 852GM/852GMV Chipset Intel® 852GM/852GMV Chipset Hub (GMCH)

Signal Description
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2. Signal Description
This section describes the GMCH signals. These signals are arranged in functional groups according to
their associated interface. The following notations are used to describe the signal type:
I
Input pin
O
Output pin
I/O
Bi-directional Input/Output pin
The signal description also includes the type of buffer used for the particular signal:
AGTL+ Open Drain GTL+ interface signal. Refer to the GTL+ I/O Specification for complete details.
The GMCH integrates AGTL+ termination resistors, and supports V_tt of 1.2-1.30 V ± 5%.
AGTL+ signals are “inverted bus” style where a low voltage represents a logical “1”.
DVO DVO buffers. These are 1.5-V tolerant
1.5 V 1.5-V compatible DC and AC Specification voltage levels
SSTL_2 Stub Series Termination Logic compatible signals. These are 2.5-V tolerant.
LVTTL Low Voltage TTL compatible signals. These are 3.3-V tolerant.
CMOS CMOS buffers. These are 3.3-V tolerant
LVDS Low Voltage Differential signal interface
Analog Analog signal interface
Ref
Voltage reference signal
Note:
System address and data bus signals are logically inverted signals. In other words, the actual values are
inverted of what appears on the system bus. This must be taken into account and the addresses and data
bus signals must be inverted inside the GMCH. All processor control signals follow normal convention.
A “0” indicates an active level (low voltage), and a “1” indicates an active level (high voltage).
Intel^® 852GM/852GMV Chipset GMCH Datasheet
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