JG82852GMSL7VP Datasheet, PDF (55/176 Pages) Intel Corporation – Intel® 852GM/852GMV Chipset Intel® 852GM/852GMV Chipset Hub (GMCH)

Register Description
R
3.8.3.
PCICMD – PCI Command Register
Address Offset:
Default Value:
Access:
Size:
04h
0006h
Read Only, Read/Write
16 bits
Since GMCH Device #0 does not physically reside on PCI_A many of the bits are not implemented.
Bit
15:10
9
8
7
6
5
4
3
2
1
Descriptions
Reserved
Fast Back-to-Back Enable (FB2B): This bit controls whether or not the master can do fast back-to-back
write. Since Device #0 is strictly a target this bit is not implemented and is hardwired to 0. Writes to this
bit position have no affect.
Default Value=0.
SERR Enable (SERRE): This bit is a global enable bit for Device #0 SERR messaging. The GMCH does
not have an SERR# signal, but communicates the SERR# condition by sending an SERR message to the
ICH4-M.
1 = Enable. GMCH is enabled to generate SERR messages over Hub Interface for specific Device 0
error conditions that are individually enabled in the ERRCMD register. The error status is reported in the
ERRSTS and PCISTS registers.
0 = SERR message is not generated by the GMCH for Device #0.
NOTE: This bit only controls SERR messaging for the Device #0. Device #1 has its own SERRE bit to
control error reporting for error conditions occurring on Device #1. The two control bits are used in a
logical OR manner to enable the SERR Hub Interface message mechanism.
Default Value=0.
Address/Data Stepping Enable (ADSTEP): Address/data stepping is not implemented in the GMCH,
and this bit is hardwired to 0. Writes to this bit position have no effect.
Default Value=0.
Parity Error Enable (PERRE): PERR# is not implemented by GMCH and this bit is hardwired to 0.
Writes to this bit position have no effect.
Default Value=0.
VGA Palette Snoop Enable (VGASNOOP): The GMCH does not implement this bit and it is hardwired
to a 0. Writes to this bit position have no effect.
Default Value=0.
Memory Write and Invalidate Enable (MWIE): The GMCH will never issue memory write and invalidate
commands. This bit is therefore hardwired to 0. Writes to this bit position will have no effect.
Default Value=0.
Special Cycle Enable (SCE): The GMCH does not implement this bit and it is hardwired to a 0. Writes to
this bit position have no effect.
Default Value=0.
Bus Master Enable (BME): The GMCH is always enabled as a master on HI. This bit is hardwired to a
“1”. Writes to this bit position have no effect.
Default Value=1.
Memory Access Enable (MAE): The GMCH always allows access to main System Memory. This bit is
not implemented and is hardwired to 1. Writes to this bit position have no effect.
Default Value=1.
Intel^® 852GM/852GMV Chipset GMCH Datasheet
55