JG82852GMSL7VP Datasheet, PDF (85/176 Pages) Intel Corporation – Intel® 852GM/852GMV Chipset Intel® 852GM/852GMV Chipset Hub (GMCH)

Register Description
R
Bit
27:26
Description
Back To Back Read-Write commands spacing (DDR, same or different rows/bank): This field determines
the RD-WR command spacing, in terms of common clocks based on the following formula: CL + 0.5xBL + TA
(rd-wr) – DQSS
DQSS: is time from write command to data and is always 1 CK
BL: is burst length which is set to 4
TA (rd-wr): is required DQ turn-around, can be set to 1, 2 or 3 CK
CL: is CAS latency, can be set to 2 or 2.5
Examples of usage:
For BL=4, with single DQ turn-around and CL=2, this field must be set to 4 CK (2+2+1-1)
Encoding CK between RD and WR commands
BL=4
00:
7
01:
6
10:
5
11:
4
NOTES:
Since reads in DDR SDRAM cannot be terminated by writes, the space between commands is not a function
of cycle length but of burst length.
25
24:15
Back To Back Read-Read commands spacing (DDR, different rows):
This field determines the RD-RD command spacing, in terms of common clocks based on the following
formula: 0.5xBL + TA(rd-rd)
BL: is burst length and can be set to 4.
TA (rd-rd): is required DQ turn-around, can be set to 1 or 2 CK
Examples of usage:
For BL=4, with single DQ turn-around, this field must be set to 3 CK (2+1)
Encoding CK between RD and RD commands
BL=4
0:
4
1:
3
NOTES:
Since a read to a different row doesn’t terminate a read, the space between commands is not a function of
cycle length but of burst length.
Reserved
Intel^® 852GM/852GMV Chipset GMCH Datasheet
85